Hardware Design for Machine Learning Acceleration

Aim

The course intends to give hands-on experience on the design of an advanced machine learning accelerator using reconfigurable hardware with a focus on performance, debugging, , memory and interaction between the hardware and software.After completion of course the student shall be able to:

• Design and integrate hardware accelerators for machine learning applications.
• Use high-level languages C/C++ for system-on-chip design.
• Integrate a system-on-chip of IP blocks to solve a specific problem.
• Debug and estimate the performance of the accelerator via simulation.
• Implement the design in an FPGA board, test functionality using testbenches, measure performance and analyze performance bottlenecks.

Content

In this course we will explore the architecture and features of modern FPGAs (Field Programable Gate Arrays) together with their application to machine learning and artificial intelligence hardware acceleration. FPGAs are a form of reconfigurable hardware in which the underlaying logic adapts to fit the algorithmic problem and they can achieve higher performance and better energy efficiency than alternative CPU/GPU hardware in certain applications. We will focus on the architecture of system-on-chip devices that combine a processor and FPGA fabric in the same chip such as the Xilinx/AMD Zynq and Versal families. While the Zynq family is characterized by the presence of programmable logic and processing system in the same device, the Versal family adds so called intelligent engines as a 2-dimensional array of VLIW (Very Long Instruction Word) programmable processors. This makes these devices a highly scalable and heterogeneous platform that requires significant engineering software and hardware skills. We will learn how to use C-based high-level synthesis to replace traditional Verilog/VHDL RTL design to create fast and efficient hardware accelerators for neural network operators within the machine learning and artificial intelligence fields. The course will cover different hardware optimization strategies and how C-based pragmas are used to control the output generated by high-level synthesis. In the labs the VITIS HLS and VIVADO synthesis and implementation tools will target a SoC Zynq FPGA that also includes an ARM-based processing system. The ARM processor acts as a host and sends and collects results from the hardware accelerator. The course requires previous knowledge on computer architecture, digital design and C/C++ based programming. Some previous experience with Python would be useful. C/C++ is used as the design language for the accelerator using state-of-the-art high-level-synthesis compilers. The accelerator is then exported as an IP block in VHDL/Verilog and integrated with other components including the ARM processor to form a functional system-on-chip. Initial simulations followed by FPGA implementation are used to verify the correct functionality and the obtained acceleration level.