TSEA53 · 6 credits · Basic level (G1N) · Datateknik, Elektroteknik
Switching Theory and Logical Design
Active · next start VT 2027
83%
passed the latest regular sitting
UPG1 · 18 Mar 2026 · 95 students
83%
passed the regular sittings, all sittings over the last 5 years
UPG1 · 95 students
39%
Harder than 39% of courses at basic level
Compared with 874 courses at the same level, ordinary exams over the last three academic years. 95 students.
Part of 2 programmes
Hand-in or lab
UPG1 Laboratory work examination
- G
- U
Main rounds
83% passed · 95 students
- 83%95
Later rounds
52% passed · 31 students
- 100%5
- 58%19
- 0%7
- Pass a later round: 52% (31 students), compared with 83% (95 students) on the ordinary exam
Show small sittings (2)
Sittings with fewer than 5 students, often credit transfers or special sittings. They are not part of any figure on this page.
- 100%1
- 100%3
Other modules
Partial exams, hand-ins and labs. They are not part of the figures at the top.
Hand-in or lab
LAB1 Laboratory work
- G
Main rounds
100% passed · 121 students
- 100%121
Later rounds
No sittings with at least 5 students.
About the course
Aim
The purpose of the course is to provide a theoretical and practical basis for the construction and troubleshooting of digital systems. After completing the course, the student should be able to:
- translate a problem statement into a theoretical model for digital circuits
- apply structured methods for the analysis and synthesis of digital circuits
- translate a design into functioning hardware
- verify the hardware against the original problem description
Content
Lectures, lessons and laboratory work cover:
- Number systems, conversions and codes
- Boolean algebra, XOR
- Combinational circuits: minimization, Karnaugh maps, NAND- and NOR-networks, tri-state, buses, incompletely specified networks, multiple-output networks
- Combinational components: adders. comparators, decoders, demultiplexers, multiplexers
- Memories, programmable Logic
- Sequential networks, state graphs, Mealy- and Moore-networks, equivalent states
- Synthesis with data flip-flops, asynchronous signals to synchronous networks, initialisation
- Synthesis with counters and shift registers
- Modelling in VHDL, simulation and synthesis of VHDL
- Examiner
- Gunnar Hjern
- Scheduled hours
- 60 h
- Main field of study
- Datateknik, Elektroteknik